Dynamic random access memories (DRAMs) have been an extremely important memory type for which there is an ever increasing need for more memory locations (increased density) per device. By far the most popular approach to making a DRAM cell is a planar cell in which a capacitor and a transistor are formed along the surface of a substrate. The typical approach for increasing cell density has been primarily to scale the planar cell as the ability to draw and process finer lines has improved.
Another approach has been to form one or both of the transistor and capacitor vertically, into the substrate. This approach has generally been referred to as trench because typically, the capacitor is formed within a "trench" which has been etched in the substrate. The trench approach is more difficult to manufacture but DRAMs using trenches have been successfully produced. The trench approach does provide more density but more difficult processing. There is thus a tradeoff analysis between the planar and trench approach. The current tradeoff favors the planar approach. Further improving the density of the trench approach would provide more favor for the trench approach and could reverse the tradeoff balance. For a simplistic example, if the yield for a trench cell was 45% and a planar cell was 90%, there would need to be twice as many die of the trench cell on a given wafer type than for the planar cell on the same wafer type for there to be the same number of good die of each cell type for a given wafer type. There are other factors also to consider such as complexity of equipment and how long it takes to process a wafer from start to finish (throughput). The improvement in density of the trench approach, however, would tend to make the tradeoff more favorable to the trench approach. There is thus a need to improve the density of the trench approach.
One of these improvement was to also make the transistor a vertical transistor as well as the capacitor a vertical capacitor. One such approach is described in article to supplied by the inventor. The approach in this article includes a field oxide region between transistors for the typical purpose of field oxide, to prevent adjacent transistors from being coupled together by a parasitic transistor. This field oxide region necessarily increases the amount of space necessary for a cell and thus reduces density.